A high-level modeling system (HLMS) allows a user to assemble, simulate, and debug an electronic circuit design. Some HLMS′, such as the System Generator HLMS from Xilinx, also allow the design to be translated into a hardware description language (HDL).
An electronic circuit design in an HLMS is generally assembled with design blocks. Each block performs a desired function in the design, and instances of the blocks are connected to accomplish the overall function of the design. For user convenience in assembling and manipulating the design, the block instances may be hierarchically arranged or nested such that a block instance may include one or more sub-block instances.
Additional tools are used in transforming the high-level design into a low-level form that is realizable in hardware. These tools provide functions of technology mapping, component placement, and signal routing. In many instances, these tools change the names of the components or elements in the design, which makes analysis challenging if the user is used to working with high-level designs.
A low-level design may be analyzed to determine whether certain objectives, such as timing constraints, have been achieved. However, the user of an HLMS may be unable to easily inspect and understand the information produced by the low-level analyzers. The difficulties arise because a low-level analyzer expresses the output information using the names it received as input or as may have been modified by the analyzer. Since the names presented by the low-level analyzer may be different from the names in the high-level modeling system, it may be difficult to make use of the analyzer output for a designer accustomed to working at the high-level provided by the HLMS.
The present invention may address one or more of the above issues.